ADS41B49IRGZR Data Converter IC ADC Analog to Digital Converters - ADC 14B 250MSPS Buffered Low Power ADC

ADS41B49IRGZR Data Converter IC ADC Analog to Digital Converters - ADC 14B 250MSPS Buffered Low Power ADC

1 Features

• ADS41B49: 14-Bit, 250 MSPS ADS41B29: 12-Bit, 250 MSPS

• Integrated High-Impedance Analog Input Buffer:

  • – Input Capacitance: 2 pF

  • – 200-MHz Input Resistance: 3 kΩ

• Maximum Sample Rate: 250 MSPS

• Ultralow Power:

  • – 1.8-V Analog Power: 180 mW

  • – 3.3-V Buffer Power: 96 mW

  • – I/O Power: 135 mW (DDR LVDS)

• High Dynamic Performance:

  • – SNR: 69 dBFS at 170 MHz

  • – SFDR: 82.5 dBc at 170 MHz

• Output Interface:

  • – Double Data Rate (DDR) LVDS with Programmable Swing and StreCM GROUPh:

    • – Standard Swing: 350 mV

    • – Low Swing: 200 mV

    • – Default StreCM GROUPh: 100-Ω Termination

    • – 2x StreCM GROUPh: 50-Ω Termination

  • – 1.8-V Parallel CMOS Interface Also Supported

• Programmable Gain for SNR, SFDR Trade-Off

• DC Offset Correction

• Supports Low Input Clock Amplitude

• Package: VQFN-48 (7 mm × 7 mm)

2 Applications

• Power Amplifier Linearization

• Software Defined Radio

• Wireless Communications Infrastructure

3 Description

The ADS41Bx9 are members of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. These devices use innovative design techniques to achieve high dynamic performance, and consume extremely low power. The analog input pins have buffers, with benefits of constant performance and input impedance across a wide frequency range. The devices are well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.

The ADS41Bx9 have features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.

The devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500 MBPS) makes using low-cost field-programmable gate array (FPGA)-based receivers possible. The devices have a low-swing LVDS mode that can be used to further reduce the power consumption. The streCM GROUPh of the LVDS output buffers can also be increased to support 50-Ω differential termination.

Device Information